EMC646SP16JS-90LL datasheet(54/65 Pages) EMLSI

54 / 65 page

EMC646SP16J

4Mx16 CellularRAM

Preliminary

Figure 43. Burst WRITE Interrupted by Burst WRITE or READ - Variable Latency Mode

Note:

1. Non-default BCR settings for burst WRITE interrupted by burst WRITE or READ in variable latency mode: Variable latency; latency code two

(three clocks); WAIT active LOW; WAIT asserted during delay. All bursts shown for variable latency; no refresh collision.

2. Burst interrupt shown on first allowable clock (i.e., after first data word written).

3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM.

CLK

ADV#

CE#

WE#

LB#/UB#

DQ[15:0] IN

Don’t Care

Undefined

A[21:0]

OE#

VIH

VIL

WAIT

VOH

VOL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

Valid

Address

tCLK

Valid

Output

tSP tHD

Valid

Address

tSP tHD

tCSP

tSP tHD

Valid

Output

Valid

Output

Valid

Output

tSP tHD

tHD

tACLK

tKOH

tCEM (Note 3)

WRITE Burst interrupted with new WRITE or READ. See Note 2.

tSP tHD

tKHTL

tCEW

tBOE

tOHZ

2nd Cycle WRITE

VOH

VOL

VIH

VIL

VIH

VIL

tSP tHD

tSP

tSP tHD

LB#/UB#

DQ[15:0] OUT

OE#

High-Z

2nd Cycle WRITE

2nd Cycle READ

tHD

VOH

VOL

High-Z

EMC646SP16JS-90LL Datasheet(PDF) 54 Page - Emerging Memory & Logic Solutions Inc

EMC646SP16JS-90LL Datasheet(HTML) 54 Page - Emerging Memory & Logic Solutions Inc

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