EMC646SP16JS-12LF datasheet(53/65 Pages) EMLSI

53 / 65 page

EMC646SP16J

4Mx16 CellularRAM

Preliminary

Figure 42. Burst READ Interrupted by Burst READ or WRITE

Note:

1. Non-default BCR settings for burst READ interrupted by burst READ or WRITE: Fixed or variable latency code two (three clocks); WAIT active

LOW; WAIT asserted during delay. All bursts shown for variable latency; no refresh collision.

2. Burst interrupt shown on first allowable clock (i.e., after the first data received by the controller).

3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM.

CLK

ADV#

CE#

WE#

LB#/UB#

DQ[15:0] OUT

Don’t Care

Undefined

A[21:0]

OE#

VIH

VIL

WAIT

VOH

VOL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

Valid

Address

tCLK

Valid

Output

tSP tHD

Valid

Address

tSP tHD

tCSP

tSP tHD

Valid

Output

Valid

Output

Valid

Output

tSP tHD

tHD

tACLK

tKOH

tCEM (Note 3)

READ Burst interrupted with new READ or WRITE. See Note 2.

tSP tHD

tKHTL

tCEW

Valid

Output

tACLK

tBOE

tOHZ

tBOE

2nd Cycle READ

VIH

VIL

VIH

VIL

VIH

VIL

LB#/UB#

DQ[15:0] IN

OE#

High-Z

tOHZ

High-Z

2nd Cycle Write

EMC646SP16JS-12LF Datasheet(PDF) 53 Page - Emerging Memory & Logic Solutions Inc

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