AT89C51IC2-SLSCM datasheet(110/146 Pages) ATMEL

110 / 146 page

110

AT89C51IC2

4301A–8051–01/04

Table 86. Default Values

After programming the part by ISP, the BSB must be cleared (00h) in order to allow the

application to boot at 0000h.

The content of the Software Security Byte (SSB) is described in Table 86 and Table 88.

To assure code protection from a parallel access, the HSB must also be at the required

level.

Table 87. Software Security Byte

The two lock bits provide different levels of protection for the on-chip code and data,

when programmed as shown in Table 88.

Mnemonic

Definition

Default value

Description

SBV

Software Boot Vector

FCh

HSB

Hardware security Byte

101x 1011b

BSB

Boot Status Byte

0FFh

SSB

Software Security Byte

FFh

Copy of the Manufacturer Code

58h

ATMEL

Copy of the Device ID #1: Family Code

D7h

C51 X2, Electrically Erasable

Copy of the Device ID #2: memories

F7h

AT89C51IC2 32KB

Copy of the Device ID #3: name and

revision

EFh

AT89C51IC2 32KB, Revision

7654

3210

------

LB1

LB0

Bit

Number

Bit

Mnemonic

Description

Reserved

Do not clear this bit.

Reserved

Do not clear this bit.

Reserved

Do not clear this bit.

Reserved

Do not clear this bit.

Reserved

Do not clear this bit.

Reserved

Do not clear this bit.

1-0

LB1-0

User Memory Lock Bits

see Table 88

AT89C51IC2-SLSCM Datasheet(PDF) 110 Page - ATMEL Corporation

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