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AT89C51RC2-3CSIM Datasheet(PDF) 61 Page - ATMEL Corporation |
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AT89C51RC2-3CSIM Datasheet(HTML) 61 Page - ATMEL Corporation |
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61 / 127 page  61 AT89C51RB2/RC2 4180C–8051–12/03 Table 48. IPL1 Register IPL1 - Interrupt Priority Register (B2h) Reset Value = XXXX X000b Bit addressable 76 54 32 1 0 - - - - - SPIL - KBDL Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2 SPIL SPI Interrupt Priority Bit see SPIH for priority level. 1- Reserved The value read from this bit is indeterminate. Do not set this bit. 0 KBDL Keyboard Interrupt Priority Bit see KBDH for priority level. |
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