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AT89C51RC2-3CSIM Datasheet(PDF) 56 Page - ATMEL Corporation |
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AT89C51RC2-3CSIM Datasheet(HTML) 56 Page - ATMEL Corporation |
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56 / 127 page  56 AT89C51RB2/RC2 4180C–8051–12/03 Registers A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. Table 43. Priority Level Bit Values If two interrupt requests of different priority levels are received simultaneously, the request of higher-priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence. IPH. x IPL. x Interrupt Level Priority 0 0 0 (Lowest) 01 1 10 2 11 3 (Highest) |
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