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AT89C51RC2-3CSIM Datasheet(PDF) 116 Page - ATMEL Corporation |
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AT89C51RC2-3CSIM Datasheet(HTML) 116 Page - ATMEL Corporation |
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116 / 127 page  116 AT89C51RB2/RC2 4180C–8051–12/03 External Data Memory Read Cycle Serial Port Timing - Shift Register Mode Table 80. Symbol Description Table 81. AC Parameters for a Fix Clock Table 82. AC Parameters for a Variable Clock ALE PSEN RD PORT 0 PORT 2 A0-A7 DATA IN ADDRESS OR SFR-P2 TAVWL TLLWL TRLAZ ADDRESS A8-A15 OR SFR P2 TRHDZ TWHLH TRLRH TLLDV TRHDX TLLAX TAVDV Symbol Parameter T XLXL Serial port clock cycle time T QVHX Output data set-up to clock rising edge T XHQX Output data hold after clock rising edge T XHDX Input data hold after clock rising edge T XHDV Clock rising edge to input data valid Symbol -M -L Units Min Max Min Max TXLXL 300 300 ns TQVHX 200 200 ns T XHQX 30 30 ns T XHDX 00 ns T XHDV 117 117 ns Symbol Type Standard Clock X2 Clock X Parameter for - M Range X Parameter for -L Range Units TXLXL Min 12 T 6 T ns TQVHX Min 10 T - x 5 T - x 50 50 ns TXHQX Min 2 T - x T - x 20 20 ns TXHDX Min x x 0 0 ns TXHDV Max 10 T - x 5 T- x 133 133 ns |
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