OR4E02-2BA352I datasheet(61/152 Pages) LATTICE

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Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

FPGA States of Operation (continued)

Reconﬁguration

To reconﬁgure the FPGA when the device is operating

in the system, a low pulse is input into PRGM or one of

the program bits in the embedded system bus control

FPGA is cleared, and the I/Os not used for conﬁgura-

tion are 3-stated with a pullup. The FPGA then samples

the mode select inputs and begins reconﬁguration.

When reconﬁguration is complete, DONE is released,

allowing it to be pulled high.

Partial Reconﬁguration

All ORCA device families have been designed to allow

a partial reconﬁguration of the FPGA at any time. This

is done by setting a bit stream option in the previous

conﬁguration sequence that tells the FPGA to not reset

all of the conﬁguration RAM during a reconﬁguration.

Then only the conﬁguration frames that are to be modi-

ﬁed need to be rewritten, thereby reducing the conﬁgu-

ration time.

Other bit stream options are also available that allow

one portion of the FPGA to remain in operation while a

partial reconﬁguration is being done. If this is done, the

user must be careful to not cause contention between

the two conﬁgurations (the bit stream resident in the

FPGA and the partial reconﬁguration bit stream) as the

second reconﬁguration bit stream is being loaded.

During a partial re-conﬁguration where the conﬁgura-

tion option is set to have the internal logic remain active

during conﬁguration the internal SLJC BIDI signals will

always be 3-stated. Previous families of ORCA FPGAs

would allow the BIDIs to continue to be under user

logic control during a partial re-conﬁguration.

Other Conﬁguration Options

There are many other conﬁguration options available to

the user that can be set during bit stream generation in

ispLEVER. These include options to enable boundary-

scan and/or the MPI and/or the programmable PLL

blocks, readback options, and options to control and

use the internal oscillator after conﬁguration.

Other useful options that affect the next conﬁguration

(not the current conﬁguration process) include options

to disable the global set/reset during conﬁguration, dis-

able the 3-state of I/Os during conﬁguration, and dis-

able the reset of internal RAMs during conﬁguration to

allow for partial conﬁgurations (see above). For more

information on how to set these and other conﬁguration

options, please see the ispLEVER documentation.

Conﬁguration Data Format

The ispLEVER Development System interfaces with

front-end design entry tools and provides tools to pro-

duce a fully conﬁgured FPGA. This section discusses

using the ispLEVER Development System to generate

conﬁguration RAM data and then provides the details

of the conﬁguration frame format.

Using ispLEVER to Generate Conﬁguration

RAM Data

The conﬁguration data bit stream deﬁnes the I/O func-

tionality, logic, and interconnections within the FPGA.

The bit stream is generated by the development sys-

tem. The bit stream created by the bit stream genera-

tion tool is a series of 1s and 0s used to write the FPGA

conﬁguration RAM. It can be loaded into the FPGA

using one of the conﬁguration modes discussed later.

In bit stream generator, the designer selects options

that affect the FPGA’s functionality. Using the output of

the bit stream generator, circuit_name.bit, the devel-

opment system’s download tool can load the conﬁgura-

tion data into the ORCA series FPGA evaluation board

from a PC or workstation.

A download cable that can be used to download from

any PC or workstation supported by ispLEVER is avail-

able. This cable allows download to an FPGA that can

be programmed via the serial conﬁguration interface

(requiring the mode pins to be set) or the JTAG bound-

ary scan interface (not requiring the setting of mode

pins). The lead device can then program other FPGAs

or FPSCs on the board via daisy-chaining.

Alternatively, a user can program a PROM (such as a

Serial ROM or a standard EPROM) and load the FPGA

from the PROM. The development system’s PROM

programming tool produces a ﬁle in .mcs, .tek or .exo

format.

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