STA335BWQS datasheet(21/72 Pages) STMICROELECTRONICS

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STA335BWQS

Functional description

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Functional description

5.1

Functional pin status

5.1.1

Power-down function

Pin PWRDN (23) is used to power down the STA335BWQS.

PWRDN = 0 (GND)

→ Power down

PWRND = 1 (VDD)

→ Normal operation

During the power-down sequence the output begins a gradual (soft) mute. After the mute

condition is reached the power stage is switched off (Hi-Z) then the master clock to all

internal hardware blocks is gated. The PLL is also switched off. The power-down sequence

takes 13 million cycles.

5.1.2

Reset function

Pin RESET (31) is used to reset the STA335BWQS.

RESET = 0 (GND)

→ Reset state

RESET = 1 (VDD)

→ Normal operation

When pin RESET is forced to 0 the power stage is switched off (Hi-Z) and the master clock

to all internal hardware blocks is gated.

Note:

RESET condition takes priority over PWRDN condition.

Table 8.

Functional pin status

Pin name

Pin #

Logic value

IC status

RESET

Reset state:

Power stage is switched off

All the registers are set to default value

RESET

Normal operation

PWRDN

Low power mode:

Power stage is switched off then the PLL is switched off

(this operation take 13 million clock cycles)

PWRDN

Normal operation

TWARN

Temperature warning indication from external power stage

TWARN

Normal operation

EAPD

Low power mode for power stage:

All internal regulators are switched off

EAPD

Normal operation

STA335BWQS Datasheet(PDF) 21 Page - STMicroelectronics

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