| Electronic Components Datasheet Search |
|
STA559BWQS Datasheet(PDF) 33 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STA559BWQS Datasheet(HTML) 33 Page - STMicroelectronics |
|
33 / 66 page ![]() STA559BWQS Register description 33/66 5.3 Configuration register C (addr 0x02) 5.3.1 DDX power output mode Table 23. DXX power output mode The DDX power output mode selects how the DDX output timing is configured. Different power devices use different output modes. 5.3.2 DDX compensating pulse size register Table 25. DXX compensating pulse size register D7 D6 D5 D4 D3 D2 D1 D0 OCRB CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0 1 0 101 1 1 Bit RW RST Name Description 0RW 1 OM0 DDX power output mode: selects configuration of DDX output. 1RW 1 OM1 Table 24. Output modes OM[1,0] Output stage - Mode 00 Drop compensation 01 Discrete output stage - Tapered compensation 10 Full power mode 11 Variable drop compensation (CSZx bits) Bit RW RST Name Description 2RW 1 CSZ0 Contra size register: when OM[1,0] = 11, this register determines the size of the DDX compensating pulse from 0 clock ticks to 15 clock periods. 3RW 0 CSZ1 4RW 1 CSZ2 5RW 0 CSZ3 Table 26. Compensating pulse size CSZ[3:0] Compensating pulse size 0000 0ns (0 tick) Compensating pulse size 0001 20ns (1 tick) Clock period compensating pulse size …… 1111 300 ns (15 tick) Clock period compensating pulse size |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |