STA559BWQS datasheet(41/66 Pages) STMICROELECTRONICS

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STA559BWQS

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5.6.3

Binary output mode clock loss detection

Table 47.

Binary output mode clock loss detection

Detects loss of input MCLK in binary mode and will output 50% duty cycle.

5.6.4

LRCK double trigger protection

Table 48.

LRCK double trigger protection

Actively prevents double trigger of LRCLK.

5.6.5

Auto EAPD on clock loss

Table 49.

Auto EAPD on clock loss

When active, will issue a power device power down signal (EAPD) on clock loss detection.

5.6.6

IC power down

Table 50.

IC power down

The PWDN register is used to place the IC in a low-power state. When PWDN is written as

0, the output will begin a soft-mute. After the mute condition is reached, EAPD will be

asserted to power down the power-stage, then the master clock to all internal hardware

expect the I2C block will be gated. This places the IC in a very low power consumption state.

Bit

RST

Name

Description

BCLE

Binary output mode clock loss detection enable

Bit

RST

Name

Description

LDTE

LRCLK double trigger protection enable

Bit

RST

Name

Description

ECLE

Auto EAPD on clock loss

Bit

RST

Name

Description

7RW

PWDN

IC power down:

0 - IC powerdown low-power condition

1 - IC normal operation

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