MC13191 Technical Data, Rev. 1.6

12

Freescale Semiconductor

6.2.2

SPI Transaction Operation

Although the SPI port of an MCU transfers data in bursts of 8 bits, the MC13191 requires that a complete

SPI transaction be framed by CE, and there will be three (3) or more bursts per transaction. The assertion

of CE to low, signals the start of a transaction. The first SPI burst is a write of an 8-bit header to the

transceiver (MOSI is valid) that defines a 6-bit address of the internal resource being accessed and

identifies the access as being a read or write operation. In this context, a write consists of data written to

the MC13191 and a read consists of data written to the SPI master. The following SPI bursts will be either

the write data (MOSI is valid) to the transceiver or read data from the transceiver (MISO is valid).

Although the SPI bus is capable of sending data simultaneously between master and slave, the MC13191

never uses this mode. The number of data bytes (payload) will be a minimum of 2 bytes and can extend to

a larger number depending on the type of access. After the final SPI burst, CE is negated to high to signal

the end of the transaction. Refer to the MC13191 Reference Manual, (MC13191RM) for more details on

SPI registers and transaction types.

An example SPI read transaction with a 2-byte payload is shown in Figure 8.

Figure 8. SPI Read Transaction Diagram

7

Pin Connections

Table 8. Pin Function Description

Pin # Pin Name

Type

Description

Functionality

1

RFIN-

RF Input

LNA negative differential input.

2

RFIN+

RF Input

LNA positive differential input.

3

Not Used

Tie to Ground.

4

Not Used

Tie to Ground.

5

PAO+

RF Output /DC

Input

Power Amplifier Positive Output. Open drain. Connect to

6

PAO-

RF Output/DC Input Power Amplifier Negative Output. Open drain. Connect to

7

SM

Test mode pin. Tie to Ground

Tie to Ground for

normal operation

CE

SPICLK

MISO

MOSI

Valid

Valid

Valid

Clock Burst

Header

Read data