M306V2EEFS datasheet(256/271 Pages) RENESAS

256 / 271 page

Rev.1.40

Oct 06, 2004 page 256 of 269

M306V2ME-XXXFP, M306V2EEFP

Table 5.8.1 Memory expansion mode and microprocessor mode (no wait) (referenced to VCC = 5 V,

VSS = 0 V at Ta = 25 oC, CM15 = “1” unless otherwise specified)

Symbol

Standard

Measuring condition

Max.

Min.

ParameterUnit

td(BCLK-AD)

Address output delay time35

th(BCLK-AD)

Address output hold time (BCLK standard)4

th(BCLK-CS)

Chip select output hold time (BCLK standard)4

td(BCLK-ALE)

ALE signal output delay time35

th(BCLK-ALE)

ALE signal output hold time

– 4ns

td(BCLK-RD)

RD signal output delay time35

th(BCLK-RD)

RD signal output hold time

td(BCLK-WR)

WR signal output delay time

th(BCLK-WR)

WR signal output hold time0

td(BCLK-DB)

Data output delay time (BCLK standard)40

th(BCLK-DB)

Data output hold time (BCLK standard)4

th(WR-DB)

Data output hold time (WR standard)(Note 2)0

td(DB-WR)

Data output delay time (WR standard)ns

(Note 1)

Note 1: Calculated according to the BCLK frequency as follows:

td(DB – WR) =

f(BCLK)

10 9

– 40

[ns]

td(BCLK-CS)

Chip select output delay time35

th(RD-AD)

Address output hold time (RD standard)0

th(WR-AD)

Address output hold time (WR standard)

2: This is standard value shows the timing when the output is off,

and does not show hold time of data bus.

Hold time of data bus is different by capacitor volume and pull-

up (pull-down) resistance value.

Hold time of data bus is expressed in

t = –CR ✕ ln (1 – VOL / VCC)

by a circuit of the right figure.

For example, when VOL = 0.2VCC, C = 30 pF, R = 1 k

Ω, hold

time of output “L” level is

t = – 30 pF ✕ 1k

Ω ✕ ln (1 – 0.2VCC / VCC)

= 6.7 ns.

DBi

Figure 5.9.1

5.8 Switching Characteristics

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