M306V2EEFS datasheet(258/271 Pages) RENESAS

258 / 271 page

Rev.1.40

Oct 06, 2004 page 258 of 269

M306V2ME-XXXFP, M306V2EEFP

Table 5.8.3 Memory expansion mode and microprocessor mode

(with wait, accessing external memory, multiplex bus area selected)

(referenced to VCC = 5 V, VSS = 0 V at Ta = 25 oC, CM15 = “1” unless otherwise specified)

Symbol

Standard

Measuring condition

Max.

Min.

ParameterUnit

td(BCLK-AD)

Address output delay time

th(BCLK-AD)

Address output hold time (BCLK standard)4

td(BCLK-CS)

Chip select output delay time35

th(BCLK-CS)

Chip select output hold time (BCLK standard)

th(RD-AD)

Address output hold time (RD standard)

(Note)

td(BCLK-RD)

RD signal output delay time35ns

th(BCLK-RD)

RD signal output hold time0

th(WR-AD)

Address output hold time (WR standard)

(Note)

td(BCLK-WR)

WR signal output delay time35ns

td(BCLK-DB)

Data output delay time (BCLK standard)

th(BCLK-DB)

Data output hold time (BCLK standard)4

td(DB-WR)

Data output delay time (WR standard)

(Note)

td(BCLK-ALE)

ALE signal output delay time (BCLK standard)

th(BCLK-ALE)

ALE signal output hold time (BCLK standard)

– 4

th(ALE-AD)

ALE signal output hold time (Adderss standard)30

th(BCLK-WR)

WR signal output hold time0

th(RD-CS)

Chip select output hold time (RD standard)

(Note)

th(WR-CS)

Chip select output hold time (WR standard)

(Note)

td(AD-RD)

Post-address RD signal output delay timens

td(AD-WR)

Post-address WR signal output delay time

tdZ(RD-AD)

Address output floating start time

th(WR-DB)

Data output hold time (WR standard)ns

(Note)

Note: Calculated according to the BCLK frequency as follows:

th(RD – AD) =

f(BCLK) ✕ 2

[ns]

th(WR – AD) =

f(BCLK) ✕ 2

10 9

[ns]

th(RD – CS) =

f(BCLK) ✕ 2

10 9

[ns]

th(WR – CS) =

f(BCLK) ✕ 2

10 9

[ns]

td(DB – WR) =

f(BCLK) ✕ 2

10 9 ✕ 3

– 40

[ns]

td(AD – ALE) =

f(BCLK) ✕ 2

– 25

[ns]

th(WR – DB) =

f(BCLK) ✕ 2

10 9

[ns]

td(AD-ALE)

ALE signal output delay time (Address standard)ns

(Note)

Figure 5.9.1

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