M306V2EEFS datasheet(264/271 Pages) RENESAS

264 / 271 page

Rev.1.40

Oct 06, 2004 page 264 of 269

M306V2ME-XXXFP, M306V2EEFP

Figure 5.10.5 Timing diagram in memory expansion mode and microprocessor mode (4)

Memory Expansion Mode and Microprocessor Mode

(When accessing external memory area with wait, and select multiplexed bus)

BCLK

CSi

td(BCLK–CS)

35ns.max

td(BCLK–AD)

35ns.max

ALE

th(BCLK–ALE)

–4ns.min

35ns.max

th(BCLK–RD)

0ns.min

th(BCLK–AD)

4ns.min

th(BCLK–CS)

4ns.min

tcyc

th(RD–CS)

th(RD–AD)

ADi

BHE

ADi

/DBi

th(RD–DB)

0ns.min

td(AD–ALE)

Read timing

td(BCLK–WR)

35ns.max

th(BCLK–WR)

0ns.min

BCLK

CSi

td(BCLK–CS)

35ns.max

td(BCLK–AD)

35ns.max

ALE

35ns.max

th(BCLK–ALE)

–4ns.min

th(BCLK–AD)

4ns.min

th(BCLK–CS)

4ns.min

tcyc

th(WR–AD)

ADi

BHE

td(BCLK–DB)

40ns.max

4ns.min

th(BCLK–DB)

td(DB–WR)

th(WR–DB)

ADi

/DBi

Write timing

Address

Measuring conditions

• VCC=5V

• Input timing voltage : Determined with VIL=0.8V, VIH=2.5V

• Output timing voltage : Determined with V OL=0.8V, VOH=2.0V

(tcyc/2)ns.min

Address

Data input

40ns.min

(tcyc/2)ns.min

td(BCLK–ALE)

td(BCLK–RD)

(tcyc/2)ns.min

th(WR–CS)

Address

td(AD–ALE)

(tcyc/2–25)ns.min

(tcyc*3/2–40)ns.min

(tcyc/2)ns.min

td(BCLK–ALE)

(tcyc/2-25)ns.min

Address

35ns.max

tSU(DB–RD)

tac3(RD–DB)

(tcyc/2)ns.min

th(ALE–AD)

30ns.min

td(AD–RD)

0ns.min

tdz(RD–AD)

8ns.max

td(AD–WR)

0ns.min

Data output

WR,WRL,

WRH

M306V2EEFS Datasheet(PDF) 264 Page - Renesas Technology Corp

M306V2EEFS Datasheet(HTML) 264 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL