M38B72FD datasheet(55/110 Pages) RENESAS

55 / 110 page

38B7 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

Timing Setting

Each timing is set by the FLDC mode register, Tdisp time set reg-

ister, Toff1 time set register, and Toff2 time set register.

(1) Tdisp time setting

The Tdisp time means the length of display timing. In non-grada-

tion display mode, it consists of the FLD display output term and

the Toff1 time. In gradation display mode, it consists of the display

output term and the Toff1 time plus a low signal output term for

dark display. Set the Tdisp time by the Tdisp counter count source

selection bit of the FLDC mode register and the Tdisp time set

n, the Tdisp time is represented as Tdisp = (n+1) ✕ t (t: count

source). When the Tdisp counter count source selection bit of the

FLDC mode register is “0” and the value of the Tdisp time set reg-

ister is 200 (C816), the Tdisp time is: Tdisp = (200 + 1) ✕ 4.0

µs (at

XIN = 4 MHz) = 804

µs. When reading the Tdisp time set register,

the counting value is read out.

(2) Toff1 time setting

The Toff1 time means a non-output (low signal output) time to pre-

vent blurring of FLD and for dimmer display. Use the Toff1 time set

smaller than Tdisp and Toff2. Supposing that the value of the Toff1

time set register is n1, the Toff1 time is represented as Toff1 =

n1 ✕ t. When the Tdisp counter count source selection bit of the

FLDC mode register is “0” and the value of the Toff1 time set reg-

ister is 30 (1E16), Toff1 = 30 ✕ 4.0

µs (at XIN = 4 MHz) = 120 µs.

Be sure to set the value of 0316 or more to the Toff1 time set reg-

ister (address 0EF616).

(3) Toff2 time setting

The Toff2 time is time for dark display. For bright display, the FLD

display output remains effective until the counter that is counting

Tdisp underflows. For dark display, however, “L” (or “off”) signal is

output when the counter that is counting Toff2 underflows. This

Toff2 time setting is valid only for FLD ports which are in the gra-

dation display mode and whose gradation display control RAM

value is “1” .

Set the Toff2 time by the Toff2 time set register. Make sure the

value set to Toff2 is smaller than Tdisp but larger than Toff1. Sup-

posing that the value of the Toff2 time set register is n2, the Toff2

time is represented as Toff2 = n2 ✕ t. When the Tdisp counter

count source selection bit of the FLDC mode register is “0” and

the value of the Toff2 time set register is 180 (B416), Toff2 = 180 ✕

4.0

µs (at XIN = 4 MHz) = 720 µs.

When bit 7 of the FLD output control register (address 0EFC16) is

set to “1”, be sure to set the value of 0316 or more to the Toff2 time

set register (address 0EF716).

Fig. 54 FLD and digit output timing

Toff1

Tdisp

Toff1

Toff2

Tdisp

•Gradation display mode is not selected

(Address 0EF416 bit 5 = “0”)

•Gradation display mode is selected and set for bright display

(Address 0EF416 bit 5 = “1” and the corresponding gradation

display control data = “0”)

Low output term for

blurring prevention

Display output term

Low output term for

blurring prevention

•Gradation display mode is selected and set for dark display

(Address 0EF416 bit 5 = “1” and the corresponding gradation

display control data = “1”)

Low output term for

dark display

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