M32C83T datasheet(84/527 Pages) RENESAS

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Page 61

7. Bus

)

(

Figure 7.5 External Bus Operation with Software Wait State (2)

BCLK

Read Signal

Write Signal

Address Bus/Data Bus(2)

Chip-Select Signal(2, 3)

Address

Address Bus

Data output

Address

Input

ALE

Bus cycle(1)

(2) Multiplexed Bus with 2 Wait States

Bus cycle(1)

BCLK

Read Signal

Write Signal

Chip-Select

Signal(2, 3)

Bus cycle(1)

(1) Separate Bus with 3 Wait States

Address

Address Bus(2)

Address

Bus cycle(1)

Data Bus

Data output

Input

BCLK

Read Signal

Write Signal

Address Bus/

Data Bus(2)

Chip-Select

Signal(2, 3)

Address

Address Bus

Data output

Address

Input

Bus cycle(1)

(3) Multiplexed Bus with 3 Wait States

Address

ALE

Bus cycle(1)

NOTES:

1. This example illustrates bus cycle length. Read cycle and write cycle may occur consecutively.

2. The address bus and chip-select signal may be extended depending on CPU state such as an

instruction queue buffer.

3. When the microcomputer continuously accesses the same external space (same CS area), the chip-

select signal may be output continuously.

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