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M32C83T Datasheet(PDF) 100 Page - Renesas Technology Corp |
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M32C83T Datasheet(HTML) 100 Page - Renesas Technology Corp |
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100 / 527 page ![]() Page 77 8 8 4 f o 6 0 0 2 , 1 3 . n a J 1 3 . 1 . v e R 1 3 1 0 - 4 3 0 0 B 9 0 J E R 8. Clock Generation Circuit ) T 3 8 / C 2 3 M , 3 8 / C 2 3 M ( p u o r G 3 8 / C 2 3 M Figure 8.11 Switching Procedure from On-chip Oscillator Clock to Main Clock 8.1.4 PLL Clock The PLL frequency synthesizer generates the PLL clock based on the main clock. The PLL clock can be used as a clock source for the CPU clock or peripheral function clock. Connect a resistor and capacitor to the VCONT pin when using the PLL frequency synthesizer. Set the PD8_6 and PD8_7 bits in the PD8 register to "0" (input mode) and the CM04 bit to "0" (the XCIN and XCOUT pins as ports). After that, connect the VCONT pin, the P86 pin, and the VSS pin to the circuit as is shown in Figure 8.12. Set the PLV00 bit in the PLV register to "1" (power to PLL). The PLL frequency synthesizer stops after reset. When the PLC07 bit is set to "1" (PLL on), the PLL frequency synthesizer starts operating. Wait 20 ms (5 V operation) to 50 ms (3.3 V operation) for the PLL clock to stabilize. The PLL clock can either be the clock output from the voltage controlled oscillator (VCO) divided-by-2 or divided-by-3. When the PLL clock is used as a clock source for the CPU clock or peripheral function clock, set each bit as is shown in Table 8.2. Figure 8.13 shows the procedure for using the PLL clock as the CPU clock source. To enter wait or stop mode, set the CM17 bit to "0" (main clock as CPU clock source). Set the PLC07 bit in the PLC0 register to "0" (PLL off) and the PLV00 bit to "0" (no power to PLL) before the microcomputer enters wait or stop mode. The VCONT and P86 pins share pins with XCIN and XCOUT pins. When the PLL frequency synthesizer is being used, the sub clock cannot be used. Switch to the main clock Determine several times whether the CM23 bit is set to "0" (main clock oscillates) Set the CM22 bit to "0" (main clock does not stop) Set the MCD register to "0816" (divide-by-8) Set the CM21 bit to "0" (main clock as CPU clock source) End CM21 to CM23 bits : Bits in CM2 register Yes No |
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