R8C2K datasheet(339/471 Pages) RENESAS

339 / 471 page

R8C/2K Group, R8C/2L Group

17. Serial Interface

Rev.1.10

Dec 21, 2007

Page 322 of 450

REJ09B0406-0110

17.1

Clock Synchronous Serial I/O Mode

In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock.

Table 17.1 lists the Clock Synchronous Serial I/O Mode Specifications. Table 17.2 lists the Registers Used and

Settings in Clock Synchronous Serial I/O Mode.

i = 0 or 2

NOTES:

1. If an external clock is selected, ensure that the external clock is “H” when the CKPOL bit in the UiC0

transfer clock), and that the external clock is “L” when the CKPOL bit is set to 1 (transmit data output

at rising edge and receive data input at falling edge of transfer clock).

2. If an overrun error occurs, the receive data (b0 to b8) of the UiRB register will be undefined. The IR

bit in the SiRIC register remains unchanged.

Table 17.1

Clock Synchronous Serial I/O Mode Specifications

Item

Specification

Transfer data format

• Transfer data length: 8 bits

Transfer clocks

• CKDIR bit in UiMR register is set to 0 (internal clock): fi/(2(n+1))

fi = f1, f8, f32 n = value set in UiBRG register: 00h to FFh

• The CKDIR bit is set to 1 (external clock): input from CLKi pin

Transmit start conditions

• Before transmission starts, the following requirements must be met(1)

- The TE bit in the UiC1 register is set to 1 (transmission enabled)

- The TI bit in the UiC1 register is set to 0 (data in the UiTB register)

Receive start conditions

• Before reception starts, the following requirements must be met(1)

- The RE bit in the UiC1 register is set to 1 (reception enabled)

- The TE bit in the UiC1 register is set to 1 (transmission enabled)

- The TI bit in the UiC1 register is set to 0 (data in the UiTB register)

Interrupt request

generation timing

• When transmitting, one of the following conditions can be selected

- The UiIRS bit is set to 0 (transmit buffer empty):

When transferring data from the UiTB register to UARTi transmit register

(when transmission starts).

- The UiIRS bit is set to 1 (transmission completes):

When completing data transmission from UARTi transmit register.

• When receiving

When data transfer from the UARTi receive register to the UiRB register

(when reception completes).

Error detection

• Overrun error(2)

This error occurs if the serial interface starts receiving the next data item

before reading the UiRB register and receives the 7th bit of the next data.

Select functions

• CLK polarity selection

Transfer data input/output can be selected to occur synchronously with the

rising or the falling edge of the transfer clock.

• LSB first, MSB first selection

Whether transmitting or receiving data begins with bit 0 or begins with bit 7

can be selected.

• Continuous receive mode selection

Receive is enabled immediately by reading the UiRB register.

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