R8C2K datasheet(341/471 Pages) RENESAS

341 / 471 page

R8C/2K Group, R8C/2L Group

17. Serial Interface

Rev.1.10

Dec 21, 2007

Page 324 of 450

REJ09B0406-0110

Figure 17.7

Transmit and Receive Timing Example in Clock Synchronous Serial I/O Mode

Transfer clock

TE bit in UiC1

TXDi

• Example of transmit timing (when internal clock is selected)

Set data in UiTB register

Transfer from UiTB register to UARTi transmit register

CLKi

TCLK

Stop pulsing because the TE bit is set to 0

TC=TCLK=2(n+1)/fi

fi: Frequency of UiBRG count source (f1, f8, f32)

n: Setting value to UiBRG register

The above applies under the following settings:

• CKDIR bit in UiMR register = 0 (internal clock)

• CKPOL bit in UiC0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock)

• UiIRS bit in UiC1 register = 0 (an interrupt request is generated when the transmit buffer is empty)

Set to 0 when interrupt request is acknowledged, or set by a program

Write dummy data to UiTB register

Transfer from UiTB register to UARTi transmit register

1/fEXT

Receive data is taken in

Read out from UiRB register

Transfer from UARTi receive register to

UiRB register

TI bit in UiC1

TXEPT bit in

UiC0 register

IR bit in SiTIC

Set to 0 when interrupt request is acknowledged, or set by a program

• Example of receive timing (when external clock is selected)

RE bit in UiC1

TE bit in UiC1

TI bit in UiC1

RI bit in UiC1

IR bit in SiRIC

CLKi

RXDi

The above applies under the following settings:

• CKDIR bit in UiMR register = 1 (external clock)

• CKPOL bit in UiC0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock)

The following conditions are met when “H” is applied to the CLKi pin before receiving data:

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