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R8C2K Datasheet(PDF) 347 Page - Renesas Technology Corp |
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R8C2K Datasheet(HTML) 347 Page - Renesas Technology Corp |
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347 / 471 page  R8C/2K Group, R8C/2L Group 17. Serial Interface Rev.1.10 Dec 21, 2007 Page 330 of 450 REJ09B0406-0110 Figure 17.11 Receive Timing Example in UART Mode UiBRG output Set to 0 when interrupt request is accepted, or set by a program • Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) The above timing diagram applies when the register bits are set as follows: • UiMR register PRYE bit = 0 (parity disabled) • UiMR register STPS bit = 0 (1 stop bit) i = 0 or 2 UiC1 register RE bit Start bit Stop bit D0 D1 D7 RXDi Transfer clock Determined to be “L” Receive data taken in Reception triggered when transfer clock is generated by falling edge of start bit Transferred from UARTi receive register to UiRB register UiC1 register RI bit SiRIC register IR bit 1 0 1 0 1 0 |
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