R8C2K datasheet(382/471 Pages) RENESAS

382 / 471 page

R8C/2K Group, R8C/2L Group

20. Flash Memory

Rev.1.10

Dec 21, 2007

Page 365 of 450

REJ09B0406-0110

20.3.2

ROM Code Protect Function

The ROM protect function prevents the contents of the flash memory from being read, rewritten, or erased by

means of the OFS register when parallel I/O mode is used.

Figure 20.3 shows the OFS Register. Refer to 14. Option Function Select Area for details of the OFS register.

The ROM code protect function is enabled by writing 0 to the ROMCP1 bit and 1 to the ROMCR bit. It disables

reading or changing the contents of the on-chip flash memory.

Once ROM code protect is enabled, the content in the internal flash memory cannot be rewritten in parallel I/O

mode. To disable ROM code protect, erase the block including the OFS register with CPU rewrite mode or

standard serial I/O mode.

Figure 20.3

OFS Register

Option Function Select Register

(1)

Symbol

Address

When Shipping

OFS

0FFFFh

FFh(3)

Bit Symbol

Bit Name

Function

NOTES:

The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not

w rite additions to the OFS register.

LVD0ON

Voltage detection 0

circuit start bit(2)

0 : Voltage monitor 0 reset enabled after hardw are

reset

1 : Voltage monitor 0 reset disabled after hardw are

reset

—

(b4)

Reserved bit

Set to 1.

b3 b2 b1 b0

b7 b6 b5 b4

WDTON

Watchdog timer start

select bit

0 : Starts w atchdog timer automatically after reset

1 : Watchdog timer is inactive after reset

—

(b1)

Reserved bit

Set to 1.

ROMCR

ROM code protect

disabled bit

0 : ROM code protect disabled

1 : ROMCP1 enabled

ROMCP1

ROM code protect bit

0 : ROM code protect enabled

1 : ROM code protect disabled

If the block including the OFS register is erased, FFh is set to the OFS register.

—

(b6)

Reserved bit

Set to 1.

CSPROINI

Count source protect

mode after reset select

bit

0 : Count source protect mode enabled after reset

1 : Count source protect mode disabled after reset

Setting the LVD0ON bit is only valid after a hardw are reset. To use the pow er-on reset, set the LVD0ON bit to 0

(voltage monitor 0 reset enabled after hardw are reset).

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