R8C2K datasheet(383/471 Pages) RENESAS

383 / 471 page

R8C/2K Group, R8C/2L Group

20. Flash Memory

Rev.1.10

Dec 21, 2007

Page 366 of 450

REJ09B0406-0110

20.4

CPU Rewrite Mode

In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU.

Therefore, the user ROM area can be rewritten directly while the MCU is mounted on a board without using a

ROM programmer. Execute the software command only to blocks in the user ROM area.

The flash module has an erase-suspend function when an interrupt request is generated during an erase operation in

CPU rewrite mode. It performs an interrupt process after the erase operation is halted temporarily. During erase-

suspend, the user ROM area can be read by a program.

In case an interrupt request is generated during an auto-program operation in CPU rewrite mode, the flash module

has a program-suspend function which performs the interrupt process after the auto-program operation is

suspended. During program-suspend, the user ROM area can be read by a program.

CPU rewrite mode has an erase write 0 mode (EW0 mode) and an erase write 1 mode (EW1 mode). Table 20.3 lists

the Differences between EW0 Mode and EW1 Mode.

Table 20.3

Differences between EW0 Mode and EW1 Mode

Item

EW0 Mode

EW1 Mode

Operating mode

Single-chip mode

Areas in which a rewrite

control program can be

executed

RAM (Rewrite control program is

executed after being transferred)

User ROM or RAM

Rewritable areas

User ROM

However, blocks which contain a rewrite

control program are excluded

Software command

restrictions

None

• Program and block erase commands

Cannot be run on any block which

contains a rewrite control program

• Read status register command

Cannot be executed

Modes after program or

erase

Read status register mode

Read array mode

Modes after read status

Read status register mode

Do not execute this command

CPU status during auto-

write and auto-erase

Operating

Hold state (I/O ports hold state before the

command is executed)

Flash memory status

detection

• Read bits FMR00, FMR06, and FMR07

in the FMR0 register by a program

• Execute the read status register

command and read bits SR7, SR5, and

SR4 in the status register.

Read bits FMR00, FMR06, and FMR07 in

the FMR0 register by a program

Conditions for transition to

erase-suspend

Set bits FMR40 and FMR41 in the FMR4

The FMR40 bit in the FMR4 register is set

to 1 and the interrupt request of the

enabled maskable interrupt is generated

Conditions for transitions to

program-suspend

Set bits FMR40 and FMR42 in the FMR4

The FMR40 bit in the FMR4 register is set

to 1 and the interrupt request of the

enabled maskable interrupt is generated

CPU clock

5 MHz or below

No restriction (on clock frequency to be

used)

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