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R8C2K Datasheet(PDF) 319 Page - Renesas Technology Corp |
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R8C2K Datasheet(HTML) 319 Page - Renesas Technology Corp |
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319 / 471 page  R8C/2K Group, R8C/2L Group 16. Timers Rev.1.10 Dec 21, 2007 Page 302 of 450 REJ09B0406-0110 Figure 16.140 TRDCR0 Register in PWM3 Mode Timer RD Control Register 0 (2) Symbol Address After Reset TRDCR0 0140h 00h Bit Symbol Bit Name Function RW NOTES: 1. 2. Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). RW CKEG1 CCLR0 RW Set to 001b (the TRD0 register cleared at compare match w ith TRDGRA0 register) in PWM3 mode. TRD0 counter clear select bits RW b3 b2 CKEG0 b1 b0 TCK2 001 b7 b6 b5 b4 Count source select bits b2 b1b0 0 0 0 : f1 0 0 1 : f2 0 1 0 : f4 0 1 1 : f8 1 0 0 : f32 1 0 1 : Do not set. 1 1 0 : fOCO40M 1 1 1 : Do not set. External clock edge select bits(1) These bits are disabled in PWM3 mode. The TRDCR1 register is not used in PWM3 mode. RW TCK1 RW TCK0 RW RW RW CCLR2 CCLR1 |
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