R8C2K datasheet(321/471 Pages) RENESAS

321 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 304 of 450

REJ09B0406-0110

Figure 16.142 Registers TRDIER0 to TRDIER1 in PWM3 Mode

Figure 16.143 TRD0 Register in PWM3 Mode

Timer RD Interrupt Enable Register i (i = 0 or 1)

Symbol

Address

After Reset

TRDIER0

0144h

11100000b

TRDIER1

0154h

11100000b

Bit Symbol

Bit Name

Function

OVIE

—

(b7-b5)

—

Nothing is assigned. If necessary, set to 0.

When read, the content is 1.

Input capture/compare match

interrupt enable bit C

0 : Disable interrupt (IMIC) by the

IMFC bit

1 : Enable interrupt (IMIC) by the

IMFC bit

IMIEC

Input capture/compare match

interrupt enable bit D

0 : Disable interrupt (IMID) by the

IMFD bit

1 : Enable interrupt (IMID) by the

IMFD bit

Overflow /underflow interrupt enable

bit

0 : Disable interrupt (OVI) by the

OVF bit

1 : Enable interrupt (OVI) by the

OVF bit

IMIEB

Input capture/compare match

interrupt enable bit A

0 : Disable interrupt (IMIA) by the

IMFA bit

1 : Enable interrupt (IMIA) by the

IMFA bit

Input capture/compare match

interrupt enable bit B

0 : Disable interrupt (IMIB) by the

IMFB bit

1 : Enable interrupt (IMIB) by the

IMFB bit

IMIEA

b7 b6 b5 b4 b3 b2

IMIED

b1 b0

Timer RD Counter 0

(1, 2)

Symbol

Address

After Reset

TRD0

0147h-0146h

0000h

Setting Range

NOTES:

2. The TRD1 register is not used in PWM3 mode.

(b8)

(b15)

Access the TRD0 register in 16-bit units. Do not access it in 8-bit units.

Function

Count a count source. Count operation is incremented.

When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1.

0000h to FFFFh

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