R8C2K datasheet(316/471 Pages) RENESAS

316 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 299 of 450

REJ09B0406-0110

Figure 16.137 TRDFCR Register in PWM3 Mode

Timer RD Function Control Register

Symbol

Address

After Reset

TRDFCR

013Ah

10000000b

Bit Symbol

Bit Name

Function

NOTES:

STCLK

External clock input select bit

Set this bit to 0 (external clock input

disabled) in PWM3 mode.

PWM3

ADTRG

ADEG

A/D trigger edge select bit

(enabled in complementary PWM mode)

This bit is disabled in PWM3 mode.

PWM3 mode select bit(2)

Set this bit to 0 (PWM3 mode) in PWM3

mode.

Normal-phase output level select bit

(enabled in reset synchronous PWM

mode or complementary PWM mode)

This bit is disabled in PWM3 mode.

Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits are set to 0 (count stops).

OLS0

Counter-phase output level select bit

(enabled in reset synchronous PWM

mode or complementary PWM mode)

This bit is disabled in PWM3 mode.

A/D trigger enable bit

(enabled in complementary PWM mode)

This bit is disabled in PWM3 mode.

CMD1

Combination mode select bits(1)

Set to 00b (timer mode, PWM mode, or

PWM3 mode) in PWM3 mode.

CMD0

b7 b6 b5 b4

When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is

enabled.

b3 b2

OLS1

b1 b0

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