R8C2K datasheet(314/471 Pages) RENESAS

314 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 297 of 450

REJ09B0406-0110

Figure 16.135 TRDSTR Register in PWM3 Mode

Timer RD Start Register

(1)

Symbol

Address

After Reset

TRDSTR

0137h

11111100b

Bit Symbol

Bit Name

Function

NOTES:

—

(b7-b4)

Nothing is assigned. If necessary, set to 0.

When read, the content is 1.

Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 16.4.12.1

TRDSTR Register of Notes on Tim er RD.

TRD1 count operation select bit

[this bit is not used in PWM3 mode]

0 : Count stops at the compare match

w ith the TRDGRA1 register

1 : Count continues after the compare

match w ith the TRDGRA1 register

—

TRD0 count operation select bit

0 : Count stops at the compare match

w ith the TRDGRA0 register

1 : Count continues after the compare

match w ith the TRDGRA0 register

CSEL0

TSTART1

TRD1 count start flag(5)

0 : Count stops(3)

1 : Count starts

TRD0 count start flag(4)

0 : Count stops(2)

1 : Count starts

b7 b6 b5 b4 b3 b2

CSEL1

b1 b0

TSTART0

When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit.

When the CSEL1 bit is set to 1, w rite 0 to the TSTART1 bit.

When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count

stops).

When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count

stops).

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