R8C2K datasheet(313/471 Pages) RENESAS

313 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 296 of 450

REJ09B0406-0110

i = 0 or 1, j = either A, B, C, or D

Table 16.47

PWM3 Mode Specifications

Item

Specification

Count sources

f1, f2, f4, f8, f32, fOCO40M

Count operations

The TRD0 register is incremented (the TRD1 is not used).

PWM waveform

PWM period: 1/fk × (m+1)

Active level width of TRDIOA0 output: 1/fk × (m-n)

Active level width of TRDIOB0 output: 1/fk × (p-q)

fk: Frequency of count source

m: Value set in the TRDGRA0 register

n: Value set in the TRDGRA1 register

p: Value set in the TRDGRB0 register

q: Value set in the TRDGRB1 register

Count start condition

1 (count starts) is written to the TSTART0 bit in the TRDSTR register.

Count stop conditions

• 0 (count stops) is written to the TSTART0 bit in the TRDSTR register

when the CSEL0 bit in the TRDSTR register is set to 1.

The PWM output pin holds output level before the count stops

• When the CSEL0 bit in the TRDSTR register is set to 0, the count

stops at compare match with the TRDGRA0 register.

The PWM output pin holds level after output change by compare

match.

Interrupt request generation

timing

• Compare match (The content of the TRDi register matches content

of the TRDGRji register.)

• The TRD0 register overflows

TRDIOA0, TRDIOB0 pin

functions

PWM output

TRDIOC0, TRDIOD0, TRDIOA1

to TRDIOD1 pin functions

Programmable I/O port

INT0 pin function

Programmable I/O port, pulse output forced cutoff signal input, or

INT0 interrupt input

Read from timer

The count value can be read by reading the TRD0 register.

Write to timer

The value can be written to the TRD0 register.

Select functions

• Pulse output forced cutoff signal input (Refer to 16.4.4 Pulse

Output Forced Cutoff.)

• Buffer Operation (Refer to 16.4.2 Buffer Operation.)

• Active level selectable by pin

m+1

TRDIOA0 output

TRDIOB0 output

(When “H” is selected as the active level)

p-q

m-n

n+1

p+1

q+1

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