R8C2K datasheet(331/471 Pages) RENESAS

331 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 314 of 450

REJ09B0406-0110

• Select with bits CMD1 to CMD0 the timing of data transfer from the buffer register to the general register.

However, transfer takes place with the following timing in spite of the value of bits CMD1 to CMD0 in the

following cases:

Value in buffer register

≥ value in TRDGRA0 register:

Transfer take place at underflow of the TRD1 register.

After this, when the buffer register is set to 0001h or above and a smaller value than the value of the

TRDGRA0 register, and the TRD1 register underflows for the first time after setting, the value is

transferred to the general register. After that, the value is transferred with the timing selected by bits CMD1

to CMD0.

Figure 16.149 Operation when Value in Buffer Register

≥ Value in TRDGRA0 Register in

Complementary PWM Mode

0000h

TRDGRD0 register

TRDIOB0 output

m+1

TRDGRB0 register

Transfer

Transfer at

underflow of TRD1

n3 > m

Transfer at

underflow of TRD1

of first setting to

n2 < m

TRDIOD0 output

m: Value set in TRDGRA0 register

The above applies under the following conditions:

• Bits CMD1 to CMD0 in the TRDFCR register are set to 11b (data in the buffer register is transferred at compare match

between registers TRD0 and TRDGRA0 in complementary PWM mode).

• Both the OSL0 and OLS1 bits in the TRDFCR register are set to 1 (active ‘H” for normal-phase and counter-phase).

Count value in TRD0

Count value in TRD1

Transfer with timing set by

bits CMD1 to CMD0

Transfer with timing set by

bits CMD1 to CMD0

Transfer

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