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R5F72115D160FPV Datasheet(PDF) 672 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 672 Page - Renesas Technology Corp |
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672 / 1228 page ![]() Section 13 Compare Match Timer (CMT) Rev. 2.00 May. 08, 2008 Page 648 of 1200 REJ09B0344-0200 13.5.3 Conflict between Byte-Write and Count-Up Processes of CMCNT Even when the count-up occurs in the T2 cycle while writing to CMCNT in bytes, the writing has priority over the count-up. In this case, the count-up is not performed. The byte data on the other side, which is not written to, is also not counted and the previous contents are retained. Figure 13.7 shows the timing when the count-up occurs in the T2 cycle while writing to CMCNTH in bytes. CMCNTH T1 T2 CMCNTH M N CMCNTL X X Peripheral clock (P φ) Address signal Internal write signal CMCNT count-up enable signal CMCSR write cycle Figure 13.7 Conflict between Byte-Write and Count-Up Processes of CMCNT 13.5.4 Compare Match Between CMCNT and CMCOR Do not set a same value to CMCNT and CMCOR while the count operation of CMCNT is stopped. |
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