R5F72115D160FPV datasheet(676/1228 Pages) RENESAS

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Section 14 Watchdog Timer (WDT)

Rev. 2.00 May. 08, 2008 Page 652 of 1200

REJ09B0344-0200

14.3

The WDT has the following registers.

Table 14.2

Abbreviation R/W

Initial

Value

Address

Access

Size

Watchdog timer counter

WTCNT

R/W

H'00

H'FFFE0002

16*

Watchdog timer control/status

WTCSR

R/W

H'18

H'FFFE0000

16*

Watchdog reset control/status

WRCSR

R/W

H'1F

H'FFFE0004

16*

Note:

For the access size, see section 14.3.4, Notes on Register Access.

14.3.1

Watchdog Timer Counter (WTCNT)

WTCNT is an 8-bit readable/writable register that is incremented by cycles of the selected clock

signal. When an overflow occurs, it generates a watchdog timer overflow signal (

WDTOVF) in

watchdog timer mode and an interrupt in interval timer mode. WTCNT is initialized to H'00 by a

power-on reset caused by the

RES pin or in software standby mode.

Use word access to write to WTCNT, writing H'5A in the upper byte. Use byte access to read

from WTCNT.

Note:

The method for writing to WTCNT differs from that for other registers to prevent

erroneous writes. See section 14.3.4, Notes on Register Access, for details.

7654321

00000000

R/W

Bit:

Initial value:

R/W:

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