R5F72115D160FPV datasheet(678/1228 Pages) RENESAS

678 / 1228 page

Section 14 Watchdog Timer (WDT)

Rev. 2.00 May. 08, 2008 Page 654 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Description

TME

R/W

Timer Enable

Starts and stops timer operation. Clear this bit to 0

when using the WDT in software standby mode or

when changing the clock frequency.

0: Timer disabled

Count-up stops and WTCNT value is retained

1: Timer enabled

4, 3

⎯

All 1

Reserved

These bits are always read as 1. The write value

should always be 1.

Clock Select

These bits select the clock to be used for the WTCNT

count from the eight types obtainable by dividing the

peripheral clock (P

φ). The overflow period that is

shown in the table is the value when the peripheral

clock (P

φ) is 40 MHz.

Bits 2 to 0

Clock Ratio

Overflow Cycle

000:

× Pφ

6.4

μs

001:

1/64

× Pφ

409.6

μs

010:

1/128

× Pφ

819.2 ms

011:

1/256

× Pφ

1.64 ms

100:

1/512

× Pφ

3.3 ms

101:

1/1024

× Pφ

6.6 ms

110:

1/4096

× Pφ

26.2 ms

2 to 0

CKS[2:0]

000

R/W

111:

1/16384

× Pφ

104.9 ms

Note: If bits CKS[2:0] are modified when the WDT is

running, the up-count may not be performed

correctly. Ensure that these bits are modified

only when the WDT is not running.

R5F72115D160FPV Datasheet(PDF) 678 Page - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 678 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL