R5F72115D160FPV datasheet(668/1228 Pages) RENESAS

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Section 13 Compare Match Timer (CMT)

Rev. 2.00 May. 08, 2008 Page 644 of 1200

REJ09B0344-0200

13.4

Interrupts

13.4.1

Interrupt Sources and DMA Transfer Requests

The CMT has channels and each of them to which a different vector address is allocated has a

compare match interrupt. When both the interrupt request flag (CMF) and the interrupt enable bit

(CMIE) are set to 1, the corresponding interrupt request is output. When the interrupt is used to

activate a CPU interrupt, the priority of channels can be changed by the interrupt controller

settings. For details, see section 6, Interrupt Controller (INTC).

Clear the CMF bit to 0 by the user exception handling routine. If this operation is not carried out,

another interrupt will be generated. The direct memory access controller (DMAC) can be set to be

activated when a compare match interrupt is requested. In this case, an interrupt is not issued to

the CPU. If the setting to activate the DMAC has not been made, an interrupt request is sent to the

CPU. The CMF bit is automatically cleared to 0 when data is transferred by the DMAC.

13.4.2

Timing of Compare Match Flag Setting

When CMCOR and CMCNT match, a compare match signal is generated at the last state in which

the values match (the timing when the CMCNT value is updated to H'0000) and the CMF bit in

CMCSR is set to 1. That is, after a match between CMCOR and CMCNT, the compare match

signal is not generated until the next CMCNT counter clock input. Figure 13.4 shows the timing of

CMF bit setting.

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