R5F72115D160FPV datasheet(664/1228 Pages) RENESAS

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Section 13 Compare Match Timer (CMT)

Rev. 2.00 May. 08, 2008 Page 640 of 1200

REJ09B0344-0200

13.2.2

Compare Match Timer Control/Status Register (CMCSR)

CMCSR is a 16-bit register that indicates compare match generation, enables or disables

interrupts, and selects the counter input clock.

CMCSR is initialized to H'0000 by a power-on reset or in software standby mode, but retains its

previous value in module standby mode.

0000000000000000

R/(W)* R/W

R/W

Bit:

Initial value:

R/W:

Note:

Only 0 can be written to clear the flag after 1 is read.

CMF

CMIE

CKS[1:0]

Bit

Bit Name

Initial

Value

R/W

Description

15 to 8

⎯

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

CMF

R/(W)* Compare Match Flag

Indicates whether or not the values of CMCNT and

CMCOR match.

0: CMCNT and CMCOR values do not match

[Clearing condition]

• When 0 is written to CMF after reading CMF = 1

1: CMCNT and CMCOR values match

CMIE

R/W

Compare Match Interrupt Enable

Enables or disables compare match interrupt (CMI)

generation when CMCNT and CMCOR values match

(CMF = 1).

0: Compare match interrupt (CMI) disabled

1: Compare match interrupt (CMI) enabled

5 to 2

⎯

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

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