R5F72115D160FPV datasheet(661/1228 Pages) RENESAS

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Section 13 Compare Match Timer (CMT)

Rev. 2.00 May. 08, 2008 Page 637 of 1200

REJ09B0344-0200

Section 13 Compare Match Timer (CMT)

This LSI has an on-chip compare match timer (CMT) consisting of a two-channel 16-bit timer.

The CMT has a16-bit counter, and can generate interrupts at set intervals.

13.1

Features

• Independent selection of four counter input clocks at two channels

Any of four internal clocks (P

φ/8, Pφ/32, Pφ/128, and Pφ/512) can be selected.

• Selection of DMA transfer request or interrupt request generation on compare match by

DMAC setting

• When not in use, the CMT can be stopped by halting its clock supply to reduce power

consumption.

Figure 13.1 shows a block diagram of CMT.

CMT

CMI0

φ/8

φ/32 Pφ/128 Pφ/512

CMI1

φ/8

φ/32 Pφ/128 Pφ/512

Control circuit

Clock selection

Channel 0

Channel 1

Clock selection

Control circuit

CMSTR:

CMCSR:

CMCOR:

CMCNT:

CMI:

Compare match timer start register

Compare match timer control/status register

Compare match constant register

Compare match counter

Compare match interrupt

[Legend]

Module bus

Bus

interface

Internal bus

Figure 13.1 Block Diagram of CMT

R5F72115D160FPV Datasheet(PDF) 661 Page - Renesas Technology Corp

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