R5F72115D160FPV datasheet(659/1228 Pages) RENESAS

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Section 12 Port Output Enable 2 (POE2)

Rev. 2.00 May. 08, 2008 Page 635 of 1200

REJ09B0344-0200

12.6

Usage Note

12.6.1

Pin Status When the WDT Issues a Power-On Reset

When a power-on reset is issued by the WDT, the pin function controller (PFC) is initialized and

the I/O ports function as general inputs (initial value).

If a power-on reset is issued by the WDT during high-impedance processing by the port output

enable (POE) signal, the I/O port pins are placed in output state for a time period of one cycle of

the peripheral clock, P

φ, until the pin functions switch to general inputs.

If a power-on reset is issued by the WDT during high-impedance processing by MTU2 or MTU2S

short detection, the I/O port pins are placed in the same status as described above.

Figure 12.5 shows the I/O port pin status when a power-on reset is issued by the WDT during

high-impedance processing by the POE input while the timer output is selected.

Timer output

Pin status

General input

Timer output

General input

High-impedance state

Timer

output

One cycle of the

peripheral clock P

POE input

PFC setting value

Power-on reset by WDT

Figure 12.5 Pin Status When Power-on Reset is Issued from Watchdog Timer

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