R5F72115D160FPV datasheet(656/1228 Pages) RENESAS

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Section 12 Port Output Enable 2 (POE2)

Rev. 2.00 May. 08, 2008 Page 632 of 1200

REJ09B0344-0200

(2)

Low-Level Detection

Figure 12.3 shows the low-level detection operation. Sixteen continuous low levels are sampled

with the sampling clock selected by ICSR1 to ICSR3. If even one high level is detected during this

interval, the low level is not accepted.

The timing when the high-current pins enter the high-impedance state after the sampling clock is

input is the same in both falling-edge detection and in low-level detection.

PB18/TIOC3B

(1)

(2)

(3)

(16)

(1)

(2)

(13)

Sampling

clock

POE input

When low level is

sampled at all points

When high level is

sampled at least once

Flag set

(

POE received)

Flag not set

High-impedance state*

8/16/128 clock

cycles

Note: * The other high-current pins and MTU2 channel 0 pins also enter the high-impedance state in the similar timing.

Figure 12.3 Low-Level Detection Operation

12.4.2

Output-Level Compare Operation

Figure 12.4 shows an example of the output-level compare operation for the combination of

TIOC3B and TIOC3D. The operation is the same for the other pin combinations.

PB18/

TIOC3B

PB19/

TIOC3D

Low level overlapping detected

High impedance state

Figure 12.4 Output-Level Compare Operation

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