R5F72115D160FPV datasheet(657/1228 Pages) RENESAS

657 / 1228 page

Section 12 Port Output Enable 2 (POE2)

Rev. 2.00 May. 08, 2008 Page 633 of 1200

REJ09B0344-0200

12.4.3

Release from High-Impedance State

High-current pins that have entered high-impedance state due to input-level detection can be

released either by returning them to their initial state with a power-on reset, or by clearing all of

the flags in bits 15 to 12 (POE8F, POE7F, POE4F, POE3F, POE1F, and POE0F) of ICSR1 to

ICSR3. However, note that when low-level sampling is selected by bits 7 to 0 in ICSR1 to ICSR3,

just writing 0 to a flag is ignored (the flag is not cleared); flags can be cleared by writing 0 to it

only after a high level is input to one of the

POE0, POE1, POE3, POE4, POE7, and POE8 pins

and is sampled.

High-current pins that have entered high-impedance state due to output-level detection can be

released either by returning them to their initial state with a power-on reset, or by clearing the flag

in bit 15 (OCF1 and OCF2) in OCSR1 and OCSR2. However, note that just writing 0 to a flag is

ignored (the flag is not cleared); flags can be cleared only after an inactive level is output from the

high-current pins. Inactive-level outputs can be achieved by setting the MTU2 and MTU2S

internal registers.

R5F72115D160FPV Datasheet(PDF) 657 Page - Renesas Technology Corp