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R5F72115D160FPV Datasheet(PDF) 688 Page - Renesas Technology Corp

Part # R5F72115D160FPV
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family
PDF  1228 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 688 Page - Renesas Technology Corp

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Section 14 Watchdog Timer (WDT)
Rev. 2.00 May. 08, 2008 Page 664 of 1200
REJ09B0344-0200
14.5.4
Manual Reset in Watchdog Timer Mode
When a manual reset occurs in watchdog timer mode, the bus cycle is continued. If a manual reset
occurs while the bus is released or during DMAC burst transfer, manual reset exception handling
will be pended until the CPU acquires the bus mastership.
However, if the duration from generation of the manual reset to the bus cycle end is equal to or
longer than the duration of the internal manual reset activated, the occurrence of the internal
manual reset source is ignored instead of being pended, and the manual reset exception handling is
not executed.



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