R5F72115D160FPV datasheet(684/1228 Pages) RENESAS

684 / 1228 page

Section 14 Watchdog Timer (WDT)

Rev. 2.00 May. 08, 2008 Page 660 of 1200

REJ09B0344-0200

14.4.3

Using Watchdog Timer Mode

1. Set the WT/

IT bit in WTCSR to 1, the type of count clock in the CKS[2:0] bits in WTCSR,

whether this LSI is to be reset internally or not in the RSTE bit in WRCSR, the reset type if it

is generated in the RSTS bit in WRCSR, and the initial value of the counter in WTCNT.

2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode.

3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent

the counter from overflowing.

4. When the counter overflows, the WDT sets the WOVF flag in WRCSR to 1, and the

WDTOVF signal is output externally (figure 14.4). The WDTOVF signal can be used to reset

the system. The

WDTOVF signal is output for 64 × Pφ clock cycles.

5. If the RSTE bit in WRCSR is set to 1, a signal to reset the inside of this LSI can be generated

simultaneously with the

WDTOVF signal. Either power-on reset or manual reset can be

selected for this interrupt by the RSTS bit in WRCSR. The internal reset signal is output for

128

× Pφ clock cycles.

6. When a WDT overflow reset is generated simultaneously with a reset input on the

RES pin,

the

RES pin reset takes priority, and the WOVF bit in WRCSR is cleared to 0.

R5F72115D160FPV Datasheet(PDF) 684 Page - Renesas Technology Corp