R5F72115D160FPV datasheet(690/1228 Pages) RENESAS

690 / 1228 page

Section 15 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 May. 08, 2008 Page 666 of 1200

REJ09B0344-0200

• Four types of interrupts: Transmit-FIFO-data-empty interrupt, break interrupt, receive-FIFO-

data-full interrupt, and receive-error interrupts are requested independently.

• When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving

power.

• The quantity of data in the transmit and receive FIFO data registers and the number of receive

errors of the receive data in the receive FIFO data register can be ascertained.

• A time-out error (DR) can be detected when receiving in asynchronous mode.

Figure 15.1 shows a block diagram of the SCIF.

[Legend]

Receive shift register

Receive FIFO data register

Transmit shift register

Transmit FIFO data register

Serial mode register

Serial control register

Serial status register

Bit rate register

Serial port register

FIFO control register

FIFO data count register

Line status register

Serial extended mode register

Internal

data bus

SCFRDR (16 stage)

Module data bus

SCFTDR (16 stage)

SCRSR

SCTSR

SCSMR

SCLSR

SCFDR

SCFCR

SCFSR

SCSCR

SCSPTR

SCBRR

Transmission/reception

control

Baud rate

generator

Clock

TXI

RXI

ERI

BRI

External clock

Parity generation

Parity check

φ/4

φ/16

φ/64

SCK

TXD

RXD

SCIF

SCRSR:

SCFRDR:

SCTSR:

SCFTDR:

SCSMR:

SCSCR:

SCFSR:

SCBRR:

SCSPTR:

SCFCR:

SCFDR:

SCLSR:

SCSEMR:

SCSEMR

Figure 15.1 Block Diagram of SCIF

R5F72115D160FPV Datasheet(PDF) 690 Page - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 690 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL