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R5F72115D160FPV Datasheet(PDF) 788 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 788 Page - Renesas Technology Corp |
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788 / 1228 page ![]() Section 16 I 2C Bus Interface 3 (IIC3) Rev. 2.00 May. 08, 2008 Page 764 of 1200 REJ09B0344-0200 16.6 Bit Synchronous Circuit In master mode, this module has a possibility that high level period may be short in the two states described below. • When SCL is driven to low by the slave device • When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pull- up resistance) Therefore, it monitors SCL and communicates by bit with synchronization. Figure 16.22 shows the timing of the bit synchronous circuit and table 16.5 shows the time when the SCL output changes from low to Hi-Z then SCL is monitored. |
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