R5F72115D160FPV datasheet(791/1228 Pages) RENESAS

791 / 1228 page

Section 16 I

2C Bus Interface 3 (IIC3)

Rev. 2.00 May. 08, 2008 Page 767 of 1200

REJ09B0344-0200

16.7

Usage Notes

16.7.1

Note on Multiple Master Usage

With multi-master used, if the transfer rate setting (CKS[3:0] in ICCR1) of I

2C in this LSI is

slower than the other masters, the SCL with unexpected width may be output in rare cases.

To prevent this problem, the transfer rate of I

2C should be specified as equal to or higher than

1/1.8 of the highest transfer rate among the other masters.

16.7.2

Note on Master Receive Mode

If ICDRR is read near the falling edge of 8th clock, the receive data will not be received in some

cases. In addition, if RCVD is set to 1 near the falling edge of 8th clock, a stop condition cannot

be issued in some cases. To prevent these errors, one of the following two methods should be

selected.

1. In master receive mode, ICDRR should be read before the falling edge of 8th clock.

2. In master receive mode, RCVD should be set to 1 and the processing should be performed in

byte units.

16.7.3

Note on Master Receive Mode with ACKBT Setting

In master receive mode operation, ACKBT should be set before the 8th falling edge of SCL in the

final data transfer during continuous data transfer. Otherwise, the slave device may overrun.

16.7.4

Note on MST and TRS Bit Status When an Arbitration was Lost

If the master transmission is set according to the MST and TRS bit settings while multiple masters

are used, the conflicting status in which the AL bit in ICSR is set to 1 in master transmit mode

(MST and TRS are set to 1) depending on the arbitration lost generation timing during TRS bit

handling instruction execution.

This problem can be avoided by the following methods.

• When multiple masters are used, the MST and TRS bits should be set by a MOV instruction.

• When an arbitration lost occurs, check if both MST and TRS bits are cleared to 0. If either or

both of MST and TRS bits are not cleared to 0, both the bits should be cleared to 0.

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