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R5F72115D160FPV Datasheet(PDF) 794 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 794 Page - Renesas Technology Corp |
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794 / 1228 page ![]() Section 17 A/D Converter (ADC) Rev. 2.00 May. 08, 2008 Page 770 of 1200 REJ09B0344-0200 • Module standby mode can be set Figure 17.1 shows a block diagram of the A/D converter. AVcc AVss AVREF AVREFVss 12-bit D/A AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 + − Comparator Sample-and- hold circuit A/D conversion control circuit AVcc AVss AVREFH AVREFL Internal data bus A/D conversion end interrupt signal (ADI) GrA A/D Sample-and- hold circuit Sample-and- hold circuit Impedance- conversion circuit Impedance- conversion circuit Impedance- conversion circuit Impedance- conversion circuit Impedance- conversion circuit Sample-and- hold circuit Offset cancel circuit Bus interface A/D trigger signal from MTU2 (TRGAN, TRG0N, TRG4AN, TRG4BN) A/D trigger signal from MTU2S (TRGAN, TRG4AN, TRG4BN) External trigger signal ( ADTRG) [Legend] ADDR: ADCR: ADANSR: ADSR: ADSTRGR: GrA: A/D data register A/D control register A/D analog input channel select register A/D status register A/D start trigger select register Group A Figure 17.1 Block Diagram of A/D Converter |
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