R5F72115D160FPV datasheet(798/1228 Pages) RENESAS

798 / 1228 page

Section 17 A/D Converter (ADC)

Rev. 2.00 May. 08, 2008 Page 774 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Description

ADIE

R/W

A/D Interrupt Enable

Enables or disables the generation of A/D conversion end

interrupts (ADI) to the CPU. Operating modes must be

changed when the ADST bit is 0 to prevent incorrect

operations.

When A/D conversion ends and the ADF bit in ADSR is

set to 1 and this bit is set to 1, ADI is sent to the CPU. By

clearing the ADF bit or the ADIE bit to 0, ADI can be

cleared.

In addition, ADIE activates the DMAC when an ADI is

generated. At this time, no interrupt to the CPU is

generated.

0: Generation of A/D conversion end interrupt is disabled

1: Generation of A/D conversion end interrupt is enabled

3, 2

⎯

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

TRGE

R/W

Trigger Enable

Enables or disables A/D conversion start by the external

trigger input (

ADTRG) or A/D conversion start triggers

from the MTU2 and MTU2S (TRGAN, TRG0N, TRG4AN,

and TRG4BN from the MTU2 and TRGAN, TRG4AN, and

TRG4BN from the MTU2S). For selection of the external

trigger and A/D conversion start trigger from the MTU2 or

MTU2S, see the description of the EXTRG bit.

0: A/D conversion start by the external trigger or an A/D

conversion start trigger from the MTU or MTU2S is

disabled

1: A/D conversion start by the external trigger or an A/D

conversion start trigger from the MTU2 or MTU2S is

enabled

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