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R5F72115D160FPV Datasheet(PDF) 800 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 800 Page - Renesas Technology Corp |
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800 / 1228 page ![]() Section 17 A/D Converter (ADC) Rev. 2.00 May. 08, 2008 Page 776 of 1200 REJ09B0344-0200 17.3.2 A/D Status Register (ADSR) ADSR is an 8-bit readable/writable register that indicates the status of the A/D converter. Bit: Initial value: R/W: 7654321 0 00000000 R R R R R R R R/(W)* Note: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Do not overwrite this bit with 0 when the value of this bit is 0. * ------- ADF Bit Bit Name Initial Value R/W Description 7 to 1 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 ADF 0 R/(W)* A/D End Flag A status flag that indicates the completion of A/D conversion. [Setting condition] • When A/D conversion on all specified channels is completed in scan mode [Clearing conditions] • When 0 is written after reading ADF = 1 • When the DMAC is activated by an ADI interrupt and ADDR is read |
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