R5F72115D160FPV datasheet(797/1228 Pages) RENESAS

797 / 1228 page

Section 17 A/D Converter (ADC)

Rev. 2.00 May. 08, 2008 Page 773 of 1200

REJ09B0344-0200

17.3.1

A/D Control Register (ADCR)

ADCR is an 8-bit readable/writable register that selects A/D conversion mode and others.

Bit:

Initial value:

R/W:

7654321

00000000

R/W

ADST

ADCS

ACE

ADIE

TRGE EXTRG

Bit

Bit Name

Initial

Value

R/W

Description

ADST

R/W

A/D Start

When this bit is cleared to 0, A/D conversion is stopped

and the A/D converter enters the idle state. When this bit

is set to 1, A/D conversion is started. In single-cycle scan

mode, this bit is automatically cleared to 0 when A/D

conversion ends on the selected single channel. In

continuous scan mode, A/D conversion is continuously

performed for the selected channels in sequence until this

bit is cleared by software, a reset, or in software standby

mode, or module standby mode.

ADCS

R/W

A/D Continuous Scan

Selects either a single-cycle or a continuous scan in scan

mode. This bit is valid only when scan mode is selected.

0: Single-cycle scan

1: Continuous scan

When changing the operating mode, first clear the ADST

bit to 0.

ACE

R/W

Automatic Clear Enable

Enables or disables the automatic clearing of ADDR after

ADDR is read by the CPU or DMAC. When this bit is set

to 1, ADDR is automatically cleared to H'0000 after the

CPU or DMAC reads ADDR. This function allows the

detection of any renewal failures of ADDR.

0: Automatic clearing of ADDR after being read is

disabled.

1: Automatic clearing of ADDR after being read is enabled.

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