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R5F72115D160FPV Datasheet(PDF) 799 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 799 Page - Renesas Technology Corp |
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799 / 1228 page ![]() Section 17 A/D Converter (ADC) Rev. 2.00 May. 08, 2008 Page 775 of 1200 REJ09B0344-0200 Bit Bit Name Initial Value R/W Description 0 EXTRG 0 R/W Trigger Select Selects the external trigger ( ADTRG) or an A/D conversion start trigger from the MTU2 or MTU2S as an A/D conversion start trigger. When the external trigger is selected (EXTRG = 1), upon input of a low-level pulse to the ADTRG pin after the TRGE bit is set to 1, the A/D converter detects the falling edge of the pulse, and sets the ADST bit in ADCR to 1. The operation which is performed when 1 is written to the ADST bit by software is subsequently performed. A/D conversion start by the external trigger input is enabled only when the ADST bit is cleared to 0. When the external trigger is used as an A/D conversion start trigger, the low-level pulse input to the ADTRG pin must be at least 1.5 A φ clock cycles in width. 0: A/D converter is started by the A/D conversion start trigger from the MTU2 or MTU2S 1: A/D converter is started by the external pin ( ADTRG) |
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