R5F72115D160FPV datasheet(888/1228 Pages) RENESAS

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Section 20 I/O Ports

Rev. 2.00 May. 08, 2008 Page 864 of 1200

REJ09B0344-0200

20.1.1

Table 20.1 lists the port A registers.

Table 20.1

Abbreviation

R/W

Initial Value

Address

Access Size

Port A data register H

PADRH

R/W

H'0000

H'FFFE3800

8, 16, 32

Port A data register L

PADRL

R/W

H'0000

H'FFFE3802

8, 16

Port A port register H

PAPRH

H'xxxx

H'FFFE381C

8, 16, 32

Port A port register L

PAPRL

H'xxxx

H'FFFE381E

8, 16

20.1.2

Port A Data Registers H, L (PADRH, PADRL)

PADRH and PADRL are 16-bit readable/writable registers that store port A data. Bits PA25DR to

PA0DR correspond to pins PA25 to PA0, respectively.

When a pin function is general output, if a value is written to PADRH or PADRL, the value is

output directly from the pin, and if PADRH or PADRL is read, the register value is returned

directly regardless of the pin state.

When a pin function is general input, if PADRH or PADRL is read, the pin state, not the register

value, is returned directly. If a value is written to PADRH or PADRL, although that value is

written into PADRH or PADRL, it does not affect the pin state. Table 20.2 summarizes PADRH

and PADRL read/write operations.

PADRH and PADRL are initialized to the respective values shown in table 20.1 by a power-on

reset. PADRH and PADRL are not initialized by a manual reset or in sleep mode or software

standby mode.

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