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R5F72115D160FPV Datasheet(PDF) 902 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 902 Page - Renesas Technology Corp |
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902 / 1228 page ![]() Section 20 I/O Ports Rev. 2.00 May. 08, 2008 Page 878 of 1200 REJ09B0344-0200 20.3.2 Port D Data Register L (PDDRL) PDDRL is a 16-bit readable/writable register that stores port D data. Bits PD15DR to PD0DR correspond to pins PD15 to PD0, respectively. When a pin function is general output, if a value is written to PDDRL, the value is output directly from the pin, and if PDDRL is read, the register value is returned directly regardless of the pin state. When a pin function is general input, if PDDRL is read, the pin state, not the register value, is returned directly. If a value is written to PDDRL, although that value is written into PDDRL, it does not affect the pin state. Table 20.8 summarizes PDDRL read/write operations. PDDRL is initialized to the respective values shown in table 20.5 by a power-on reset, but is not initialized by a manual reset or in sleep mode or software standby mode. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: PD15 DR PD14 DR PD13 DR PD12 DR PD11 DR PD10 DR PD9 DR PD8 DR PD7 DR PD6 DR PD5 DR PD4 DR PD3 DR PD2 DR PD1 DR PD0 DR |
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