R5F72115D160FPV datasheet(1003/1228 Pages) RENESAS

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Section 21 Flash Memory

Rev. 2.00 May. 08, 2008 Page 979 of 1200

REJ09B0344-0200

Table 21.15 Error Codes

Code

Description

H'00

No error

H'11

Sum check error

H'21

Non-matching device code error

H'22

Non-matching clock mode error

H'24

Bit-rate selection failure

H'25

Input frequency error

H'26

Frequency multiplier error

H'27

Operating frequency error

H'29

Block number error

H'2A

Address error

H'2B

Data length error (size error)

H'51

Erasure error

H'52

Non-erased error

H'53

Programming error

H'54

Selection processing error

H'80

Command error

H'FF

Bit-rate matching acknowledge error

21.8.2

Areas for Storage of the Procedural Program and Data for Programming

In the descriptions in the previous section, storable areas for the programming/erasing procedure

programs and program data are assumed to be in on-chip RAM. However, the procedure programs

and data can be stored in and executed from other areas (e.g. external address space) as long as the

following conditions are satisfied.

1. The on-chip programming/erasing program is downloaded from the address set by FTDAR in

on-chip RAM, therefore, this area is not available for use.

2. The on-chip programming/erasing program will use 128 bytes or more as a stack. Make sure

this area is reserved.

3. Since download by setting the SCO bit to 1 will cause the MATs to be switched, it should be

executed in on-chip RAM.

4. The flash memory is accessible until the start of programming or erasing, that is, until the

result of downloading has been decided.

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